Overview
Design Verification Engineer Jobs in Bristol – England – UK at Tessolve
Title: Design Verification Engineer
Company: Tessolve
Location: Bristol – England – UK
Category: Software Development, IT/Tech
Job Description:Design Verification Engineer
Location:EU/UK (Preferably Bristol, UK or Munich, Germany)
Ifyour skills, experience, and qualifications match those in this job overview, do not delay your application.
Company Overview:Tessolve Semiconductors is a leading Design and Test Engineering Service Company with over 3000 employees globally. We specialize in turnkey ASIC solutions, providing end-to-end support from design to packaged parts. Our expertise spans pre-silicon and post-silicon domains, ensuring efficient silicon bring-up and product realization. With a strongfocus on innovation, we invest in R&D initiatives such as 5G, mmWave, and Silicon Photonics.
Additionally, we offer comprehensive embedded product design services across various industries. Trusted by Tier 1 clients and top semiconductor companies, Tessolve has a global presence with offices in key locations worldwide.
Job Summary:We are seeking an experienced Verification Engineer tojoin ourdynamicteamfocused on developing and verifying non-volatile memory IP. The successful candidate will be responsible for designing and implementing test benches, creating agents, developing and adapting tests for new NVM IP features, and ensuring comprehensive verification coverage using System Verilog and Universal Verification Methodology (UVM).
Key Responsibilities:
Develop sophisticated test benches to verify the functionality of non-volatile memory IP.
Design and implement agents to facilitatecommunicationbetween the test environment and the design under test.
Adapt existing tests and create new ones to verify new features of the NVM IP.
Execute tests and demonstrate that relevant test cases are passing accurately.
Define verification coverage metrics to ensure both structural and functional coverage goals are met.
Perform testbench qualification using Certitude or similar methodologies.
Document verification results thoroughly, including test plans, reports, and coverage metrics.
Provide evidence of test case success and verification coverage attainment.
Ensure that test benches meet the quality standards required by TSMC or other relevant stakeholders.
Collaborate effectively withcross-functional teamsincluding design, software, and validation engineers to achieve project goals.
Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
Minimum 5 years of proven experience in Digital IP verification using System Verilog and UVM.
Strong understanding of ASIC/FPGA design and verification methodologies.
Proficiency in scripting languages such as Python, Perl, or Tcl is desirable.
Excellentcommunication skillsand ability to work collaboratively in afast-paced environment.
Experience with silicon bring-up and post-silicon validation is a plus.
Ability to travel occasionally to Bristol or Munich for on-site visits if required.
Benefits:
Competitive compensation package.
Comprehensive benefitsincluding health insurance, retirement plans, and more.
Electricwork environmentfosteringcontinuous learning,skill development, and growth opportunities.
Opportunity to work on cutting-edge technologies and projects with global impact.
At Tessolve, we are committed to fostering a workplace that embraces and celebratesdiversityin all its forms. We believe thatdiverseteams driveinnovation, creativity, and success. We are dedicated to creating aninclusiveenvironment where all employees, regardless …
